This application is based on Japanese Patent Application 2001-094582, filed on Mar. 29, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to semiconductor memories and their driving methods, and more particularly to non-volatile semiconductor memories which store data by trapping electrons in an insulating film, and to its driving methods.
2. Description of the Related Art
In a non-volatile semiconductor memory such as an electrically erasable and programmable ROM (EEPROM) and a collectively and electrically erasable flash memory, a memory cell having a double gate structure of a floating gate and a control gate is generally used. Complicated manufacture processes for forming the double gate structure become an obstacle to micro patterning of semiconductor memories. Semiconductor memories using as a charge storing film an insulating film such as silicon nitride in place of a floating gate has been paid attention. A semiconductor memory of this structure stores data by capturing (trapping) charges in the insulating film such as silicon nitride.
As a semiconductor memory of this structure, a SONOS type memory is known. The gate insulating film of an FET constituting each cell of a SONOS type memory has a three-layer structure having a silicon nitride film sandwiched between silicon oxide films. Data is written by injecting electrons into the silicon nitride film, and data is erased by draining electrons.
As compared to a floating gate type memory, a SONOS type memory has a simpler gate structure so that it is suitable for realizing a memory cell of a micro size. However, a sufficiently large number of rewrite operations is not still possible and SONOS type memories are not in practical use.
It is an object of the present invention to provide semiconductor memories and their driving methods, capable of increasing the number of rewrite operations.
According to one aspect of the present invention, there is provided a semiconductor memory comprising: a semiconductor substrate; first and second impurity diffusion regions disposed in partial surface layers of the semiconductor substrate and being spaced apart by some distance; a gate electrode formed above a channel region defined between the first and second impurity diffusion regions; a gate insulating film disposed between the channel region and the gate electrode, of the gate insulating film, a portion disposed at least in a partial area along the longitudinal direction of a path interconnecting the first and second impurity diffusion regions, having a lamination structure of a first insulating film, a charge trap film and a second insulating film sequentially stacked in this order, the charge trap film being made of insulating material easier to trap electrons than the first and second insulating films; and a control circuit for performing a hole drain operation of draining holes trapped in each film between the gate electrode and the channel region or at an interface between adjacent films, by applying a hole drain voltage to the gate electrode, the hole drain voltage being higher than a voltage applied to either the first or second impurity diffusion region.
By draining holes trapped in each film between the gate electrode and the channel region or at an interface between adjacent films, it becomes possible to prevent the write speed and erase speed from being lowered even if a rewrite operation is repeated.
According to another aspect of the present invention, there is provided a semiconductor memory comprising: a semiconductor substrate; first and second impurity diffusion regions disposed in partial surface layers of the semiconductor substrate and being spaced apart by some distance; a gate electrode formed above a channel region defined between the first and second impurity diffusion regions; a gate insulating film disposed between the channel region and the gate electrode, of the gate insulating film, a portion disposed at least in a partial area along the longitudinal direction of a path interconnecting the first and second impurity diffusion regions, having a lamination structure of a first insulating film, a charge trap film and a second insulating film sequentially stacked in this order, the charge trap film being made of insulating material easier to trap electrons than the first and second insulating films; and a control circuit for applying a same voltage to the first and second impurity diffusion regions and a first positive voltage to the gate electrode, the first positive voltage being higher than the voltage applied to the first and second impurity diffusion regions.
By applying the first voltage to the gate electrode, it becomes possible to drain holes trapped in each film between the gate electrode and the channel region or at an interface between adjacent films. It is therefore possible to prevent the write speed and erase speed from being lowered even if a rewrite operation is repeated.
According to another aspect of the present invention, there is provided a semiconductor memory comprising: a semiconductor substrate; a plurality of bit lines formed on the semiconductor substrate, the bit lines extending along a first direction and disposed in parallel; a plurality of word lines disposed on the semiconductor substrate, the word lines extending along a second direction crossing the first direction and being disposed in parallel and electrically insulated from the bit lines at each cross point between the bit lines and the word lines; FET""s disposed in cross areas between each stripe area between a pair of adjacent bit lines and a corresponding word line, each of the FET""s including a pair of impurity diffusion regions of a first conductivity type, a channel region between the impurity diffusion regions, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, of the gate insulating film, a portion disposed at least in a partial area along the longitudinal direction of a path interconnecting the pair of impurity diffusion regions, having a lamination structure of a first insulating film, a charge trap film and a second insulating film sequentially stacked in this order, the charge trap film being made of insulating material easier to trap electrons than the first and second insulating films, the pair of impurity diffusion regions being connected to a corresponding pair of the bit lines, and the gate electrode being connected to a corresponding one of the word lines; and a control circuit for draining holes trapped in each film between the gate electrode and the channel region or at an interface between adjacent films, by applying a first voltage to the plurality of bit lines and applying a second voltage to the plurality of word lines, the second voltage being higher than the first voltage.
By draining holes trapped in each film between the gate electrode and the channel region or at an interface between adjacent films, it becomes possible to prevent the write speed and erase speed from being lowered even if a rewrite operation is repeated.
According to another aspect of the present invention, there is provided a method of driving a semiconductor memory, wherein: the semiconductor memory comprises: a semiconductor substrate; first and second impurity diffusion regions disposed in partial surface layers of the semiconductor substrate and being spaced apart by some distance; a gate electrode formed above a channel region defined between the first and second impurity diffusion regions; and a gate insulating film disposed between the channel region and the gate electrode, of the gate insulating film, a portion disposed at least in a partial area along the longitudinal direction of a path interconnecting the first and second impurity diffusion regions, having a lamination structure of a first insulating film, a charge trap film and a second insulating film sequentially stacked in this order, the charge trap film being made of insulating material easier to trap electrons than the first and second insulating films, and the method comprises a hole drain step of draining holes trapped in each film between the gate electrode and the channel region or at an interface between adjacent films, by applying a hole drain voltage to the gate electrode, the hole drain voltage being higher than a voltage applied to either the first or second impurity diffusion region.
By draining holes trapped in each film between the gate electrode and the channel region or at an interface between adjacent films, it becomes possible to prevent the write speed and erase speed from being lowered even if a rewrite operation is repeated.
According to another aspect of the present invention, there is provided a semiconductor memory comprising: a semiconductor substrate; a plurality of bit lines formed on the semiconductor substrate, the bit lines extending along a first direction and disposed in parallel; a plurality of word lines disposed on the semiconductor substrate, the word lines extending along a second direction crossing the first direction and being disposed in parallel and electrically insulated from the bit lines at each cross point between the bit lines and the word lines; FET""s disposed in cross areas between each stripe area between a pair of adjacent bit lines and a corresponding word line, each of the FET""s including a pair of impurity diffusion regions of a first conductivity type, a channel region between the impurity diffusion regions, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, the gate insulating film being disposed at least in a partial area along the longitudinal direction of a path interconnecting the pair of impurity diffusion regions and having a lamination structure of a first insulating film, a charge trap film and a second insulating film sequentially stacked in this order, the charge trap film being made of insulating material easier to trap electrons than the first and second insulating films, the pair of impurity diffusion regions being connected to a corresponding pair of the bit lines, and the gate electrode being connected to a corresponding one of the word lines; and a control circuit for performing an erase operation, a hole drain operation, an erase judgment operation, a write operation and a write judgment operation, the erase operation draining electrons trapped in each charge trap film of the FET""s by applying a first voltage to each of the plurality of bit lines and applying a negative erase voltage lower than the first voltage to each of the plurality of word lines, the hole drain operation draining holes trapped in each film between the gate electrode and the channel region of each of the FET""s or at an interface between adjacent films, by applying a second voltage to each of the plurality of bit lines and applying a positive hole drain voltage higher than the second voltage to each of the plurality of word lines, the erase judgment operation applying a third voltage across a pair of bit lines corresponding to a selected FET among the FET""s and applying an erase judgment voltage to a corresponding word line, to compare a current flowing between the corresponding pair of bit lines with a reference current and judge whether the selected FET is in an erase completion state or in an erase incompletion state, the write operation applying a fourth voltage across a pair of bit lines corresponding to a selected FET among the FET""s and applying a write voltage to a corresponding work line, to trap electrons in the charge trap film of the selected FET, and the write judgment operation applying a fifth voltage across a pair of bit lines corresponding to a selected FET among the FET""s and applying a write judgment voltage to a corresponding word line, to compare a current flowing between the corresponding pair of bit lines with a reference current and judge whether the selected FET is in a write completion state or in a write incompletion state, wherein the control circuit executes: a step of performing the erase operation; a step of performing the hole drain operation after the erase operation; and a step of selecting each of the FET""s subjected to the erase operation and performing the erase judgment operation, and if there is even one FET in the erase incompletion state, repeating the erase operation and the hole drain operation until all FET""s enter the erase completion state.
Since the hole drain operation is performed in succession after the erase operation, it is possible to effectively drain holes accumulated during the erase operation.
According to another aspect of the present invention, there is provided the semiconductor memory in which the control circuit executes: a step of performing the erase operation; a step of selecting each of the FET""s subjected to the erase operation and performing the erase judgment operation, and if there is even one FET in the erase incompletion state, repeating the erase operation until all FET""s enter the erase completion state; and a step of performing the hole drain operation if a judgment result by the erase judgment operation indicates that all FET""s enter the erase completion state.
Since the hole drain operation is performed after all FET""s enter the erase completion state, prolongation of the erase time to be caused by the hole drain operation can be suppressed.
According to another aspect of the present invention, there is provided the semiconductor memory in which the control circuit executes: a first step of sequentially selecting each FET from all FET""s to be written and performing the write judgment operation for each selected FET, and if the selected FET is in the write incompletion state, performing the write operation for the selected FET; a second step of performing the hole drain operation; and a third step of repeating the first and second steps if there is even one FET in the write incompletion state.
Since the hole drain operation is performed in succession after the write operation, holes accumulated during the write operation can be efficiently drained.
According to another aspect of the present invention, there is provided the semiconductor memory in which the control circuit executes: a first step of performing the hole drain operation; a second step of sequentially selecting each FET from all FET""s to be written and performing the write judgment operation for each selected FET, and if the selected FET is in the write incompletion state, performing the write operation for the selected FET; and a third step of repeating the second step if there is even one FET in the write incompletion state.
Since the hole drain operation is performed before the write operation, holes accumulated during the erase operation before the write operation can be efficiently drained.
According to another aspect of the present invention, there is provided the semiconductor memory in which the control circuit executes: a first step of sequentially selecting each FET from all FET""s to be written and performing the write judgment operation for each selected FET, and if the selected FET is in the write incompletion state, performing the write operation for the selected FET; a second step of repeating the first step if there is even one FET in the write incompletion state; and a third step of performing the hole drain operation if all FET""s to be written enter the write completion state.
Since the hole drain operation is performed after all FET""s enter the write completion state, prolongation of the write time to be caused by the hole drain operation can be suppressed.
As above, by draining holes accumulated in the laminated gate insulating film, it becomes possible to prevent the write speed and erase speed from being lowered even if a rewrite operation is repeated.